
# #########################################################################
#© Copyright 2021 Xilinx, Inc.

#Licensed under the Apache License, Version 2.0 (the "License");
#you may not use this file except in compliance with the License.
#You may obtain a copy of the License at

#    http://www.apache.org/licenses/LICENSE-2.0

#Unless required by applicable law or agreed to in writing, software
#distributed under the License is distributed on an "AS IS" BASIS,
#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#See the License for the specific language governing permissions and
#limitations under the License.
# ###########################################################################


set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets -of [get_pins design_1_i/static_region/clk_wiz_0/inst/clkout1_buf/O]]

set_property IOSTANDARD DIFF_POD12_DCI [get_ports {C0_DDR4_SLR1_dqs_c[0]}]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports {C0_DDR4_SLR1_dqs_t[0]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {C0_SYS_CLK_SLR1_clk_n[0]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {C0_SYS_CLK_SLR1_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {C0_DDR4_SLR1_ck_c[0]}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {C0_DDR4_SLR1_ck_t[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports C0_DDR4_SLR1_reset_n]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dm_n[0]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[0]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[1]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[2]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[3]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[4]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[5]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[6]}]
set_property IOSTANDARD POD12_DCI [get_ports {C0_DDR4_SLR1_dq[7]}]
set_property IOSTANDARD SSTL12_DCI [get_ports C0_DDR4_SLR1_act_n]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[10]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[11]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[12]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[13]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[14]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[15]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[16]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[2]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[3]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[4]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[5]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[6]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[7]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[8]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_adr[9]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_ba[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_ba[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_bg[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_bg[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_cke[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_cs_n[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {C0_DDR4_SLR1_odt[0]}]
set_property SLEW FAST [get_ports C0_DDR4_SLR1_act_n]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[10]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[11]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[12]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[13]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[14]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[15]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[16]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[2]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[3]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[4]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[5]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[6]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[7]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[8]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_adr[9]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_ba[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_ba[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_bg[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_bg[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_ck_c[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_ck_t[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_cke[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_cs_n[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dm_n[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[1]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[2]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[3]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[4]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[5]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[6]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dq[7]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dqs_c[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_dqs_t[0]}]
set_property SLEW FAST [get_ports {C0_DDR4_SLR1_odt[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports C0_DDR4_SLR1_act_n]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[16]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_adr[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_ba[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_ba[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_bg[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_bg[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_ck_c[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_ck_t[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_cke[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_cs_n[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dm_n[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dq[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dqs_c[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_dqs_t[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {C0_DDR4_SLR1_odt[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dm_n[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[1]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[2]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[3]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[4]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[5]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[6]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dq[7]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dqs_c[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {C0_DDR4_SLR1_dqs_t[0]}]




set_property PACKAGE_PIN AU18 [get_ports C0_DDR4_SLR1_act_n]
set_property PACKAGE_PIN BE20 [get_ports {C0_DDR4_SLR1_adr[0]}]
set_property PACKAGE_PIN AY20 [get_ports {C0_DDR4_SLR1_adr[10]}]
set_property PACKAGE_PIN BA20 [get_ports {C0_DDR4_SLR1_adr[11]}]
set_property PACKAGE_PIN BB18 [get_ports {C0_DDR4_SLR1_adr[12]}]
set_property PACKAGE_PIN BC18 [get_ports {C0_DDR4_SLR1_adr[13]}]
set_property PACKAGE_PIN BB19 [get_ports {C0_DDR4_SLR1_adr[14]}]
set_property PACKAGE_PIN BC19 [get_ports {C0_DDR4_SLR1_adr[15]}]
set_property PACKAGE_PIN BA17 [get_ports {C0_DDR4_SLR1_adr[16]}]
set_property PACKAGE_PIN BF20 [get_ports {C0_DDR4_SLR1_adr[1]}]
set_property PACKAGE_PIN BF17 [get_ports {C0_DDR4_SLR1_adr[2]}]
set_property PACKAGE_PIN BF16 [get_ports {C0_DDR4_SLR1_adr[3]}]
set_property PACKAGE_PIN BE19 [get_ports {C0_DDR4_SLR1_adr[4]}]
set_property PACKAGE_PIN BF19 [get_ports {C0_DDR4_SLR1_adr[5]}]
set_property PACKAGE_PIN BC20 [get_ports {C0_DDR4_SLR1_adr[6]}]
set_property PACKAGE_PIN BD20 [get_ports {C0_DDR4_SLR1_adr[7]}]
set_property PACKAGE_PIN BD18 [get_ports {C0_DDR4_SLR1_adr[8]}]
set_property PACKAGE_PIN BD17 [get_ports {C0_DDR4_SLR1_adr[9]}]
set_property PACKAGE_PIN BB17 [get_ports {C0_DDR4_SLR1_ba[0]}]
set_property PACKAGE_PIN AW18 [get_ports {C0_DDR4_SLR1_ba[1]}]
set_property PACKAGE_PIN AY18 [get_ports {C0_DDR4_SLR1_bg[0]}]
set_property PACKAGE_PIN AY17 [get_ports {C0_DDR4_SLR1_bg[1]}]
set_property PACKAGE_PIN BE18 [get_ports {C0_DDR4_SLR1_ck_t[0]}]
set_property PACKAGE_PIN BE17 [get_ports {C0_DDR4_SLR1_ck_c[0]}]
set_property PACKAGE_PIN AV18 [get_ports {C0_DDR4_SLR1_cke[0]}]
set_property PACKAGE_PIN AV19 [get_ports {C0_DDR4_SLR1_cs_n[0]}]
set_property PACKAGE_PIN AR18 [get_ports {C0_DDR4_SLR1_dm_n[0]}]
set_property PACKAGE_PIN AN19 [get_ports {C0_DDR4_SLR1_dq[0]}]
set_property PACKAGE_PIN AN18 [get_ports {C0_DDR4_SLR1_dq[1]}]
set_property PACKAGE_PIN AN20 [get_ports {C0_DDR4_SLR1_dq[2]}]
set_property PACKAGE_PIN AP20 [get_ports {C0_DDR4_SLR1_dq[3]}]
set_property PACKAGE_PIN AP18 [get_ports {C0_DDR4_SLR1_dq[4]}]
set_property PACKAGE_PIN AP17 [get_ports {C0_DDR4_SLR1_dq[5]}]
set_property PACKAGE_PIN AL20 [get_ports {C0_DDR4_SLR1_dq[6]}]
set_property PACKAGE_PIN AL19 [get_ports {C0_DDR4_SLR1_dq[7]}]
set_property PACKAGE_PIN AM19 [get_ports {C0_DDR4_SLR1_dqs_t[0]}]
set_property PACKAGE_PIN AM18 [get_ports {C0_DDR4_SLR1_dqs_c[0]}]
set_property PACKAGE_PIN AU19 [get_ports {C0_DDR4_SLR1_odt[0]}]
set_property PACKAGE_PIN AV20 [get_ports C0_DDR4_SLR1_reset_n]
set_property PACKAGE_PIN AY19 [get_ports {C0_SYS_CLK_SLR1_clk_p[0]}]
set_property PACKAGE_PIN BA19 [get_ports {C0_SYS_CLK_SLR1_clk_n[0]}]

